SiFive has been working with GPU giant Nvidia on porting its CUDA software stack to RISC-V, and integrating its NVLink Fusion ...
The ESP32 S31 Devkit brings a 320 MHz dual-core RISC-V processor to your next IoT project. Find out if the missing 5 GHz ...
SiFive debuted its BigSky SF-2U870 2U server platform at Hot Chips, delivering 32 P870 RISC-V cores, 256GB DDR5 memory, and ...
World's Fastest and Lowest Power 64-bit RISC-V now runs Linux, Zephyr, and FreeRTOS.SUNNYVALE, CA / ACCESS Newswire / August ...
The two companies, both long-time partners of Arm, are extending their collaboration on wearables with a RISC-V Snapdragon Wearable platform to power the next-generation Wear OS solutions. “What about ...
Earlier this month, Qualcomm announced it was working with Google on a RISC-V Wear OS chip. The Android team today provided an update on RISC-V adoption, including an initial timeline and emulator ...
If you’re closely following the semiconductor space, you will be pleased to know that Synopsys, Inc. has made a significant announcement this week. With the introduction of the new RISC-V ARC-V ...
RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set ...
ARM is the most successful microprocessor architecture on the planet, with its licensees shipping billions of chips a year. But a rival has emerged in the past few years called RISC-V, a new kind of ...
Today, Google and Qualcomm announced an extension of their partnership to bring RISC-V-based systems-on-chips (SoCs) to market with support for Wear OS, a version of Android for smartwatches and ...